The escalating demand for high density and performance imposes severe requirements on semiconductor fabrication technology, particularly interconnection technology in terms of providing reliable low R×C (resistance×capacitance) interconnect patterns with higher electromigration resistance, wherein submicron vias, contacts and trenches have high aspect ratios.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the R×C delay caused by the interconnect wiring increases.
The dramatic decrease in feature sizes into the deep submicron regime has spurred the transition from aluminum (Al)-based to copper (Cu)-based interconnect technology. This technological evolution has come about through the adoption of damascene and dual-damascene process flows, typically employing electrolytic Cu-plating followed by chemical mechanical polishing (CMP) techniques. The technological benefits of Cu, such as reduced R×C delay are quite clear. However, various reliability issues are engendered by resorting to Cu-based interconnect technology, particularly electromigration issues, resistance issues, stress migration issues and stress-induced voiding. Conventional practices involve forming a damascene opening in an interlayer dielectric, depositing a barrier layer, such as tantalum nitride, lining the opening and on the surface of the interlayer dielectric, filling the opening with Cu or Cu alloy, conducting CMP and then forming a silicon nitride capping layer on the exposed surface of the Cu or Cu alloy. Adhesion problems of the silicon nitride capping layer to the upper surface of the inlaid Cu or Cu alloy has led to peeling and adverse device performance including decreased electromigration resistance.
Attempts to provide a tantalum (Ta) capping layer for Cu-based interconnects for improved adhesion have not been free of problems. For example, it was found that Ta capping layers for Cu have led to high via resistance, poor electromigration and stress migration performance and various processing problems. Upon experimentation and investigation, it was determined that the amount of Ta on top of Cu to achieve an electromigration benefit is only 40 Å. However, in order to reliably ensure that the minimum thickness of Ta is on all Cu lines after CMP, it is necessary to etch a recess into the Cu of approximately 400 Å and deposit approximately the same thickness of Ta. Because of the CMP dishing effects for wide Cu lines, the Ta will be thinned to a greater extent on the wide lines resulting in nearly the full thickness of Ta on the narrow lines and less than 100 Å on wide lines, thereby meeting the minimum thickness requirement of 40 Å. With improved etch and CMP processes, the recess and Ta thickness can be reduced. In subsequent processes, vias are formed to the Ta capped Cu lines. The resistivity of the Ta capped metal will add to the via resistance and detract from the benefit of the Ta capped solution compared to not having a Ta cap.
If the Ta cap layer is etched over the Cu in the area of the via during the via etch processing step, several problems are generated. Firstly, it is difficult to etch Ta, and such etching increases manufacturing costs. Such Ta etching also results in the formation of voids in the Cu under the via, causes Cu contamination and causes undesirable corner bevelling.
One such conventional technique is illustrated in FIGS. 1A through 1G, wherein similar features are denoted by like reference characters. Adverting to FIG. 1, a dielectric layer 11 is formed overlying a substrate 10. For simplicity, various components, such as transistors, are not illustrated. An opening 12 is then formed in the dielectric layer 11, as shown in FIG. 1B. Subsequently, a diffusion barrier layer 13, such as Ta or tantalum nitride, is deposited, and Cu or a Cu alloy 14 is deposited to fill the opening and form an over-burden on the upper surface of dielectric layer 11, as shown in FIG. 1C. CMP is then implemented forming the structure illustrated in FIG. 1D having inlaid Cu 15. The upper surface of inlaid Cu 15 is then etched to form a recess 16, as illustrated in FIG. 1E. A capping layer 17, such as Ta, is then deposited as illustrated in FIG. 1F, followed by CMP resulting in the structure illustrated in FIG. 1G comprising inlaid Cu 15 with Ta capping layer 18 thereon. Interconnects formed by such methodology are attendant with various problems such as high via resistance, electromigration, stress migration and voiding.
Accordingly, there exists a need for improved Cu interconnects with capping layers exhibiting reduced via resistance, improved electromigration and stress migration performance and reduced voiding. There also exists a need for simplified methodology enabling obtention of such objectives.